The present invention relates to integrated circuit devices and more particularly integrated circuit memory devices and methods for programming the same.
A variety of nonvolative integrated circuit (semiconductor) memory device types are known. One such nonvolatile semiconductor memory device that is capable of being electrically programmed, erased and read, NOR-type flash memory devices, are typically used in applications where information is read at a high speed, as such memories may support high frequency program and read operations relative to other types of nonvolatile memory devices.
FIG. 1 is a cross-sectional view illustrating a conventional flash memory cell 10. The flash memory cell 10 includes a source region 3 and a drain region 4, which are formed of N+ impurities and spaced apart from each other in a P-type semiconductor substrate (or bulk) 2. A gate oxide film 7, having a thickness less than 100 Å, is formed on a channel region between the source and drain regions 3, 4 of the semiconductor substrate 2. A floating gate 6 is formed on the gate oxide film 7. An interlayer dielectric film 9, such as an oxide/nitride/oxide (ONO) film, is formed on the floating gate 6, and a control gate 8 is formed on the interlayer dielectric film 9. For the structure of the flash memory cell 10, voltage terminals Vs, Vg, Vd, and Vb are shown as electrically connected to the source region 3, the control gate 8, the drain region 4, and the semiconductor substrate 2, respectively, in order to apply voltages thereto during programming, erasing, and reading operations and/or to read voltages therefrom.
The flash memory device 10 of FIG. 1 is typically programmed by channel hot electron (CHE) injection, toward a floating gate 6, generated in a channel area adjacent to the drain region 4. The CHE injection is typically induced by grounding the source region 3 and the P type semiconductor substrate 2, and applying a high voltage, of about 10V, to the control gate electrode Vg. In order to generate the hot electrons from the drain region 4, an appropriate positive voltage, such as about 5V to about 6V is applied thereto. When the flash memory cell 10 is programmed by applying voltages, negative charges are generally accumulated in the floating gate 6. The negative charges stored in the floating gate function to increase a threshold voltage of the programmed flash memory cell during a reading operation.
After programming of the flash memory cell, one known problem is a drain turn-on phenomenon that may become a major problem affecting the reliability of the flash memory cell and its operational characteristics.
As described above, to program a memory cell by means of the effect of the CHE injection, a high voltage of about 10V is applied to a wordline (i.e., the control gate) of a selected memory cell and a voltage of about 5V is applied to a bitline (namely, the drain) of a selected memory cell. During this operation, in deselected memory cells connected to the same bitline with the selected memory cell, although the wordline is grounded, a voltage from 0.7V to 0.8 V can be coupled to the floating gate 6 due to coupling capacitance (where a coupling rate is about 0.1) between the drain 4 and the floating gate 6. As a result, a considerable amount of sub-threshold leakage current may flow through the deselected memory cells. This is typically referred to as a drain turn-on problem. The greater the number of memory cells connected to the bitline in common, the more the sub-threshold leakage current generally flows through the deselected memory cells during a programming operation. When an excessive drain turn-on problem occurs, a undesirable voltage drop may occur along the bitline. This may cause a program voltage applied to a drain of the selected cell to be reduced, which may result in the deterioration of programming reliability.